Integrated circuits and other electrical circuits or devices, such as for example a flip flop, may be susceptible to generating metastable output signals (e.g., an undefined or invalid output signal or that requires an indeterminate amount of time to generate a valid output). For example, when an asynchronous signal enters a given clock domain via a flip flop, there is a possibility of metastability if the asynchronous signal does not meet setup and hold specifications required by the flip flop relative to a clock signal.
A common approach to reduce metastability susceptibility utilizes two flip flops in series so that any metastability in the first flip-flop will have time to resolve by the time the next clock edge arrives at the second flip flop. A drawback of this approach is that the asynchronous signal has a delay of an additional clock cycle, with a worst case input latency of approximately two clock cycles and a best case input latency of approximately one clock cycle.
Another approach to reduce the susceptibility of a flip flop to metastability is to increase the gain of the flip flop circuit so that a metastable situation will likely resolve into a legal state sooner. A drawback of this approach is that the worst case (e.g., infinitely long metastability) or near worst case metastable situations generally take too long to resolve into a legal output state due to the amplification limitations for a very small signal value. As a result, there is a need for improved techniques to reduce metastable susceptibility.